1. Field of the Invention
This invention relates to signal voltage detection circuit having a differential amplifier for detecting an input signal voltage and a latch circuit for holding therein a detection result.
2. Description of Related Art
In driver integrated circuits (ICs) for driving power switching devices including, but not limited to, metal oxide semiconductor (MOS) transistors and insulated gate bipolar transistors (IGBTs), signal voltage detection circuitry is used for error detection and the like, by way of example.
FIG. 13 is an exemplary configuration of one prior known signal voltage detection circuit 10 of the type stated above. A differential amplifier 11 has a pair of driver transistors N1, N2, to which a reference voltage Vref and a signal voltage Vin to be detected are input respectively. In order to take out or derive an output current which corresponds to a detection output of this differential amplifier 11, a current mirror circuit 12 is provided. A change in output current of the current mirror circuit 12 is detected by a current-to-voltage conversion circuit 13, which includes a resistor R1 and a transistor MN1 for detection of its terminal voltage. An output of this current-voltage conversion circuit 13 is transferred via an inverter X1 toward a latch circuit 14 and is then held therein.
FIG. 14 is an operation timing diagram of the signal voltage detector circuit 10. When the input signal voltage Vin becomes higher in potential than the reference voltage Vref (at a time point t0), a collector current of the driver transistor N2 of the differential amplifier 11 changes from zero to a constant current. Upon receipt of the detection output of this differential amplifier 11, a drain current flows in P-channel MOS transistors MP1, MP2 which make up a current mirror circuit 12. In responding to receipt of an output voltage of the MOS transistor MP2, a voltage generates across the both terminate ends of the resistor R1 whereby the N-channel MOS transistor MN1 turns on. Thus, the input level of the inverter X1 potentially drops down at xe2x80x9cLowxe2x80x9d or xe2x80x9cLxe2x80x9d level, permitting a pulse of xe2x80x9cHighxe2x80x9d or xe2x80x9cHxe2x80x9d levelxe2x80x94say, H pulsexe2x80x94to be input to the latch circuit 14, resulting in retention of a latch output which is represented by Vout=L.
Even when the signal voltage Vin becomes potentially lower than the reference voltage Vref (at a time point t1), the data held in the latch circuit 14 is kept unchanged. The latch circuit 14""s hold data will be reset in response to a potential change of a reset signal RST to H level (at t2).
FIG. 15 shows another signal voltage detection circuit 20. This circuit includes its differential amplifier 21, which has an NPN transistor N1 to which the reference voltage Vref is input and a parallel combination of NPN transistors N21, N22 to which two signal voltages Vin1, Vin2 are input respectively. These driver transistors are operatively associated with a load, which is an active load. More specifically, PNP transistors P1, P2 for use as the load are connected to make up a current mirror circuit. The differential amplifier 21 generates a detection output, which is amplified by a voltage amplifying unit 22 with large-amplitude operability and is then sent forth via inverters X1, X2 to a latch circuit 23 and held therein.
FIG. 16 is an operation timing diagram of this signal voltage detector circuit 20. When either one of the input signal voltages Vinl, Vin2 becomes higher in potential than the reference voltage Vref (at time point t0), the collector current of a corresponding one of the driver transistors N21, N22 of the differential amplifier 21 changes from zero to a constant current. Upon receipt of this change, a PNP transistor P3 turns on causing the collector current to flow therein, resulting in an H pulse being obtained at a terminal of resistor R1. Whereby, a voltage of Vout=L is latched in the latch circuit 23.
Even when the signal voltage Vin potentially decreases below the reference voltage Vref (at time point t1), the data held at the latch circuit 23 is kept unchanged. The latch circuit 23""s hold data will be reset in response to a potential change of the reset signal RST to H level (at t2).
The signal voltage detector circuits 10 and 20 of FIGS. 13 and 15 are both associated with risks of operation failures or malfunction occurring due to the influence of power supply noises. A timing diagram of the signal voltage detector circuit 10 of FIG. 13 in the case of occurrence of such malfunction is shown in FIG. 17; a timing diagram of the FIG. 15 detector circuit 20 in a similar case is shown in FIG. 18.
Firstly, in the signal voltage detector circuit 10 of FIG. 13, suppose that the power supply voltage Vcc potentially drops down by a certain degree xcex94V at a time point t10 as shown in FIG. 17. In response to receipt of this potential drop-down, the current of a current source I1 of the differential amplifier 11 also decreases accordingly. And, when the power supply voltage initiates to recover at a time point t11, a displacement current rushes to flow in a relatively large collector capacitance of the driver transistor N2. This in turn causes a drain current to flow in the P-channel MOS transistors MP1, MP2 of the current mirror circuit 12. Owing to the current of MOS transistor MP2, the terminal voltage of resistor R1 increases in potential. When this voltage goes beyond the threshold voltage of NMOS transistor MN1, this MOS transistor MN1 turns on resulting in the voltage Vout=L of latch circuit 14 being latched unintentionally.
In the signal voltage detector circuit 20 of FIG. 15, assume that the power supply voltage Vcc potentially decreases by xcex94V at time point t10 as shown in FIG. 18. In this case, the current of current source I1 of the differential amplifier 21 also decreases. Simultaneously, the PNP transistors P1, which make up the current mirror with the PNP transistor P2 and is flowing a constant current, also decreases in collector current thereof. Upon potential recovery of the power supply voltage from time point t11, the collector current of one load transistor P1 recovers up to the constant current while including a displacement current for charge-up of the collector capacitance of driver transistor N1. At the other load transistor P2, a collector current flows therein as a displacement current used to charge up the large collector capacitance of driver transistors N21, N22, causing a base current of the transistor P3 to be pulled out of it. In responding thereto, an H pulse generates at the terminal of resistor R1 and is then supplied to the latch circuit 23. This would result in the voltage Vout=L being latched in latch circuit 23, although not specifically required.
As previously stated, the signal voltage detector circuit of FIG. 13 or 15 is encountered with the risk of unwanted occurrence of operation errors or malfunction due to power noises because of the presence of the collector capacitance of more than one driver transistor used. The driver-transistor collector capacitance stays harmless with respect to ordinary or standard signal detection operations. However, in the event that the power supply voltage recovers to its normally expected potential level once after rapid or xe2x80x9cspikexe2x80x9d-like drop-down due to externally attendant noises or else, the displacement current for chargeup of the collector capacitance flows in accordance with a potential change of the supply voltage without regard to the absence of any input to the differential amplifier. This displacement current flow can cause malfunction.
More practically, the circuit of FIG. 13 is faced with a problem as to the inequality or xe2x80x9cimbalancexe2x80x9d of parasitic capacitances associated with the drain side of P-channel MOS transistors MP1, MP2 making up the current mirror circuit 12. Whereas the large collector capacitance of driver transistor N2 enters at the drain of MOS transistor MP1, the drain of MOS transistor MP2 is less in parasitic capacitance. Due to this, the displacement current of driver transistor N2 which happens to flow in power supply voltage recovery events causes operation errors or malfunction.
On the other hand, the circuit of FIG. 15 suffers from a problem as to the imbalance of the parasitic capacitances associated with the drain side of PNP transistors P1, P2 making up the current mirror load of the differential amplifier 21. More specifically, while the differential amplifier 21 employs a single driver transistor N1 to which the reference voltage Vref is input, its signal voltage input side is such that the parallel-coupled two separate driver transistors N21, N22 are provided. The result of this is that the load transistor P2 is greater than load transistor P1 in drain-side parasitic capacitance value. Due to this parasitic capacitance inequality or xe2x80x9cnonequilibrium,xe2x80x9d the displacement current flowing in one driver transistor N1 and a total displacement current flowing in the other driver transistors N21, N22 are such that the latter is greater than the former in power supply voltage recovery events. In other words, the differential amplifier 21 behaves to operate improperly as if it detects an input signal in the supply voltage recovery events. This can cause malfunction.
A signal voltage detection circuit is provided to have a differential amplifier having first and second driver transistors to which a reference voltage and a signal voltage to be detected are input respectively, a current-mirror circuit configured to generate an output current corresponding to a detection output of the differential amplifier, a current-to-voltage conversion circuit configured to convert a change in output current of the current mirror circuit into a voltage and output the voltage converted, a latch circuit to which an output of the current-to-voltage conversion circuit is transferred and in which the output is held, and a capacitive load element connected to an input node of the current-to-voltage conversion circuit.